Title :
Delay estimation and optimization of logic circuits: a survey
Author :
Fujita, Masahiro ; Murgai, Rajeev
Author_Institution :
Adv. CAD Dept., Fujitsu Labs. of America Inc., Santa Clara, CA, USA
Abstract :
Logic synthesis has two stages of optimization: technology-independent and technology-dependent. This paper surveys state-of-the-art methods for estimation and optimization of delays of logic circuits at the technology-independent stage. Although at this stage we cannot completely predict final delays after technology mapping, there exist reasonably accurate estimation techniques. Final delays can be reduced with optimization techniques that use such estimation
Keywords :
circuit optimisation; combinational circuits; delays; directed graphs; logic CAD; combinational logic circuits; delay estimation; directed graphs; logic circuit optimisation; logic synthesis; survey; technology mapping; technology-dependent; technology-independent; Circuit synthesis; Combinational circuits; Delay estimation; Laboratories; Logic circuits; Logic design; Optimization methods; Predictive models; State estimation; Timing;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600053
