DocumentCode
2998290
Title
Cost minimization of partitioning circuits with complex resource constraints in FPGAs
Author
Lin, Yu-Chung ; Tseng, Su-Fen ; Hung, Yu-Shan ; Hsieh, Tsai-Ming
Author_Institution
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
fYear
2000
fDate
2000
Firstpage
556
Lastpage
559
Abstract
In this paper, we formulated a new cost minimization partition problem with complex resource constraints in large FPGAs and proposed a maximum matching and ILP based algorithm to solve it. The ILP solver, LINGO, is employed to find the number of the FPGA chips of each type to minimize the total cost. In order to get a smaller cut-size partition, we proposed a new vertex ordering matching algorithm to partition the given circuit. Experimental results on the MCNC LGSynth91 benchmark show that circuit partition with multiple resource types obtained by our algorithm has 21% lower cost on average than that using simple resource type FPGA. The proposed vertex ordering method reduces the cost by 19% compared with the method without vertex ordering considerations
Keywords
field programmable gate arrays; integer programming; linear programming; logic CAD; logic partitioning; minimisation; FPGA partitioning; ILP based algorithm; ILP solver; LINGO; MCNC LGSynth91 benchmark; circuit partitioning; complex resource constraints; cost minimisation; cost minimization partition problem; cut-size partition; large FPGAs; maximum matching algorithm; vertex ordering matching algorithm; Costs; Field programmable gate arrays; Libraries; Logic circuits; Logic devices; Logic gates; Minimization methods; Partitioning algorithms; System performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location
Tianjin
Print_ISBN
0-7803-6253-5
Type
conf
DOI
10.1109/APCCAS.2000.913560
Filename
913560
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