A design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder

In this paper, a VLSI architecture for DPCM Hybrid Coding Loop (DHCL), which consists of 2D-DCT, quantization, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the DHCL is designed to handle macroblock data within 1320 cycles and suitable for MPEG-2 video encoder accepting NTSC and PAL image formats. Only single 1-D DCT/IDCT is used for the design instead of 2-D DCT and IDCT to reduce the hardware size, and 3-bit serial distributed arithmetic architecture is adopted for 1-D IDCT to reduce the processing time in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed designs can be operated on 80 MHz clock. The area is 50% smaller than the previous methods with 2D-DCT and IDCT. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification