Lattice strain design in W/WN/poly-Si gate DRAM for improving data retention time

A lattice strain design based on a novel model drastically improves the data retention property of DRAMs fabricated through a polymetal gate (W/WN/Poly-Si) process. We clarified that vacancy-type stacking faults are located along the metallurgical p-n junction at the gate edge in tail-mode bits with respect to data retention time. The origin of the vacancy-type stacking faults appeared to be a combination of residual vacancies induced by ion implantation and the compressive lattice strain generated by STI and gate mechanical stresses. To relax the lattice strain, we carefully controlled the internal stresses in polymetal gate and STI materials. As a result, the data retention time was up to twice that with the conventional process.