A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology

For the first time, a new DRAM cell layout as the key enabler for future DRAM shrink generations based on deep trench (DT) technologies with a planar array device is presented. The work describes the full integration scheme in 70nm technology and the major technology features of the ´checkerboard (CKB)´ layout. The new layout is beneficial for lithography and high aspect ratio etch processes. In addition, the high degree of symmetry enables easily the integration of a self aligned trench bottling process on a [100] rotated substrate with an outstanding utilization of area for the capacitor. Further capacitance enhancement up to 50% is achieved for the first time in a trench process by introduction of hemispherical silicon grains (HSG) with high k dielectric material (Al₂O₃). Additionally, a new self aligned trench-cell connection (single sided buried strap) technique with a novel isolation trench (IT) pre fill process will be presented in the paper.