The optimal synchronous cyclo-static array: A multiprocessor supercomputer for digital signal processing

A fine grain parallelism multiprocessor, for digital signal processing, is currently under development and construction. The architecture is the outgrowth of theoretical work on optimal multiprocessor realizations of digital signal processing algorithms. The architecture specifically supports systolic, data driven, MIMD and cyclo-static processor realizations. The emphasis is on cyclo-static realizations, which are a class of solutions for which compilers have been designed to generate implementations that achieve several optimality criteria. An unconventionally large interprocessor communications bandwidth is provided in order to support the ability to practically achieve optimal solutions.