Title :
Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices
Author :
Severi, S. ; Anil, K.G. ; Henson, K. ; Lauwers, A. ; Veloso, A. ; de Marneffe, J.F. ; Ramos, J. ; Eyben, P. ; Vandervost, W. ; Jurczak, M. ; Biesemans, S. ; De Meyer, K. ; Pawlak, J.B. ; Duffy, R. ; Lindsay, R. ; Camillo-Castillo, R.A. ; Dachs, C.
Author_Institution :
IMEC Interuniversity Microelectron. Center, Leuven, Belgium
Abstract :
This paper reports on the successful integration of truly diffusion-less (less-than-650°C) junction formation by SPER in pMOSFETs in combination with Ni-FUSI gates for the first time. The obtained drive currents are 355 μA/μm for an off-state of 10 μA/μm at Vdd= -1.2V and 1.4nm EOT SiON. We demonstrate that the gate de-activation problem associated with SPER is effectively solved by the use of the FUSI gate electrode. Super halo profiles are obtained with SPER, which opens up the halo design space for accurate SCE control. The junction leakage is greatly reduced by engineering the damage region away from the junction depletion region.
Keywords :
MOSFET; diffusion barriers; semiconductor device metallisation; semiconductor junctions; 45 nm; FUSI gate; PMOS transistors; SPER gate; accurate SCE control; diffusion-less junctions; gate de-activation problem; halo design space; junction depletion region; junction leakage; pMOSFET; physical gate length devices; super halo profiles; CMOS technology; Doping; Electrodes; MOSFETs; Microelectronics; Plasma temperature; Rapid thermal annealing; Silicon; Space technology; Thermal resistance;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419076
