A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays

An optically differential reconfigurable gate array VLSI (ODRGA-VLSI) presents the advantage that it can be reconfigured more rapidly than other optically reconfigurable gate arrays (ORGAs). In an ORGA, reconfiguration contexts are stored in a holographic memory, which is addressed by a laser array, and read as light. The reconfiguration speed is proportional to the light intensity received in each photodiode on an ORGA-VLSI. In addition, the light intensity from a holographic memory is inversely proportional to the number of its lighting bits corresponding to bits of ´1´ from the diffraction characteristic of a holographic memory. Therefore, the bit-by-bit programmability of ODRGA-VLSI allows more rapid reconfiguration than for other ORGAs because the light power can be focused onto a reprogrammed area instead of a much larger area. However, the reconfiguration circuit to support bit-by-bit reconfiguration occupies a large implementation area of an ODRGA-VLSI chip. Therefore, a new dynamic reconfiguration circuit has been introduced into ODRGA-VLSIs to reduce the implementation area to realize a high gate-count ODRGA-VLSI. In this paper, the VLSI implementation of the dynamic reconfiguration circuit is shown using 0.35 mum CMOS process technology; a comparison to results from other optical reconfiguration circuits is presented.