DocumentCode
2998955
Title
A New Architecture for H.264 Variable Block Size Motion Estimation
Author
Yang, Chunlei ; Luo, Rong ; Yang, Huazhong
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing
Volume
2
fYear
2006
fDate
6-9 Aug. 2006
Firstpage
132
Lastpage
136
Abstract
In an H.264 video encoder, motion estimation (ME) is the most time-consuming component. Several fast ME algorithms have been proposed to reduce the complexity of integer pixel ME (IME) computation, but few of them considered IME and fractional pixel ME (FME) together. Given the possibility of performance improvement through designing both IME and FME at the same time, a new hardware architecture is proposed for variable block size motion estimation with full search at 1/4 pixel accuracy. With the search range (SR) of [-20, +19] in both horizontal and vertical direction, the new architecture will save more than 50% computation time compared with full search algorithm (FS), while the cost is 50% increase of the sum of absolute differences (SAD) in average. The hardware implementation can achieve real-time operation at a frequency of 15 MHz for CIF format frame at 30 Hz.
Keywords
encoding; motion estimation; video coding; H.264 variable block size motion estimation; H.264 video encoder; ME algorithms; computation time; fractional pixel ME; frequency 15 MHz; frequency 30 Hz; full search algorithm comparison; hardware architecture; hardware implementation; integer pixel ME; real-time operation; sum-of-absolute differences; Acceleration; Circuits; Computer architecture; Costs; Frequency; Hardware; Motion estimation; Partitioning algorithms; Strontium; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location
San Juan
ISSN
1548-3746
Print_ISBN
1-4244-0172-0
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2006.382226
Filename
4267304
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