High performance analog and digital PLL design

An high performance phase-locked-loop (PLL) design method is discussed. In this context high performance means a high order PLL with efficient noise reduction and accurate frequency response achievements. Both analog PLL (APLL) and digital PLL (DPLL) designs may be obtained through the proposed technique. The method allows any order PLL but is especially useful for high-order PLLs because of its difficult design. An explicit formalism for PLL design is established and APLL and DPLL models are also presented. High order design examples are discussed. Experimental results obtained through DPLL realization on a fixed point digital signal processor (DSP) and APLL realization with a commercially available circuit are presented, discussed and compared. Finally, conclusions are drawn.