A Systematic Error Model of High-Resolution Pipelined Analog-to-Digital Converters

This work presents a systematic error model of high- resolution pipelined analog-to-digital converters (ADCs) implemented in MATLAB. Many errors limit linearity or noise performance of high-resolution ADCs, such as sampling distortion, slew-rate (SR) limiting, closed-loop gain variation of amplifiers, capacitor mismatch, clock jitter and thermal noise. All errors mentioned above are analyzed and modeled in a set of explicit mathematic expressions. Simulation results based on this model are compared with measured results of a 10-bit prototype ADC.