A Systematic Error Model of High-Resolution Pipelined Analog-to-Digital Converters

Author

Chen, Tingqian ; Yao, Bingkun ; Xu, Jun ; Ren, Junyan

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai

Volume

2

fYear

2006

fDate

6-9 Aug. 2006

Firstpage

158

Lastpage

161

Abstract

This work presents a systematic error model of high- resolution pipelined analog-to-digital converters (ADCs) implemented in MATLAB. Many errors limit linearity or noise performance of high-resolution ADCs, such as sampling distortion, slew-rate (SR) limiting, closed-loop gain variation of amplifiers, capacitor mismatch, clock jitter and thermal noise. All errors mentioned above are analyzed and modeled in a set of explicit mathematic expressions. Simulation results based on this model are compared with measured results of a 10-bit prototype ADC.

Keywords

analogue-digital conversion; clocks; jitter; measurement errors; thermal noise; MATLAB; capacitor mismatch; clock jitter; closed-loop gain variation; explicit mathematic expressions; high-resolution ADC; high-resolution pipelined analog-to-digital converters; sampling distortion; slew-rate limiting; systematic error model; thermal noise; word length 10 bit; Analog-digital conversion; Capacitors; Clocks; Jitter; Linearity; MATLAB; Mathematical model; Performance gain; Sampling methods; Strontium;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on

Conference_Location

San Juan

ISSN

1548-3746

Print_ISBN

1-4244-0172-0

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2006.382233

Filename

4267311