FPGA implementation of digital timing recovery in software radio receiver

Author

Wu, Yik-Chung ; Ng, Tung-Sang

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ., China

fYear

2000

fDate

2000

Firstpage

703

Lastpage

707

Abstract

This paper describes an implementation of an all-digital timing recovery scheme. Squaring nonlinearity is employed to generate the timing estimate and an IIR is used to extract the spectral component at symbol rate. Hardware design is performed using VHDL and realized in FPGA. The whole design can be fitted into an Altera EPF1OK70 FPGA chip, with 95.5% utilization of logic elements and 22% utilization of memory bits. The implementation exploits features of FPGA, which enable easy implementation of look up table and variable data precision at different nodes

Keywords

IIR filters; field programmable gate arrays; hardware description languages; matched filters; synchronisation; table lookup; Altera EPF1OK70; FPGA implementation; IIR; VHDL; digital timing recovery; hardware design; logic elements; look up table; memory bits; software radio receiver; spectral component; squaring nonlinearity; symbol rate; timing estimate; variable data precision; Clocks; Digital filters; Field programmable gate arrays; Hardware; IIR filters; Interpolation; Receivers; Software radio; Table lookup; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on

Conference_Location

Tianjin

Print_ISBN

0-7803-6253-5

Type

conf

DOI

10.1109/APCCAS.2000.913617

Filename

913617