TMS 320C25 based enhanced 32 kbps ADPCM transcoder

Author

Jain, V.K. ; Skrzypkowiak, S.S. ; Heathcock, R.B.

Author_Institution

Dept. of Electr. Eng., South Florida Univ., Tampa, FL, USA

fYear

1988

fDate

11-14 Apr 1988

Firstpage

635

Abstract

The CCITT recommendation, G.721 for a 64 kbps PCM to 32 kbps ADPCM transcoder algorithm does not easily lend itself to implementation on general purpose digital signal processors. The authors present a bit-for-bit compatible realization of the algorithm and a functional real time test bed for algorithm modifications. The hardware of the unit, USF32-2 is built around a single TMS320C25 microprocessor and has added circuitry to decrease computation time and facilitate testing. The base algorithm and enhanced version can be selectively compared. The encoder/decoder requires a total of 1301 clock cycles, but can be compressed to 1250, thereby enabling one to run both the encoder and the decoder on a single TMS320C25 processor

Keywords

code standards; codecs; computerised signal processing; encoding; microprocessor chips; pulse-code modulation; 32 kbits/s; 64 kbits/s; ADPCM transcoder; CCITT recommendation; PCM; TMS320C25 microprocessor; USF32-2; algorithm modifications; base algorithm; computation time; digital signal processors; encoder/decoder; functional real time test bed; testing; Arithmetic; Circuit testing; Clocks; Decoding; Hardware; Microprocessors; Phase change materials; Registers; Signal processing algorithms; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1988. ICASSP-88., 1988 International Conference on

Conference_Location

New York, NY

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1988.196665

Filename

196665