DocumentCode
2999193
Title
Performance improvement in a binary phase comparator type PLL frequency synthesizer
Author
Obote, Shigeki ; Sumi, Yasuaki ; Kitai, Naoki ; Fukui, Yutaka ; Itoh, Yoshio
Author_Institution
Tottori Univ., Japan
Volume
4
fYear
1999
fDate
36342
Firstpage
419
Abstract
In a phase locked loop (PLL) frequency synthesizer with a binary phase comparator, ringing is hard to suppress. In this paper, we propose a PLL frequency synthesizer with a modified binary phase comparator which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results
Keywords
CMOS digital integrated circuits; digital phase locked loops; frequency synthesizers; phase comparators; PLL frequency synthesizer; PSpice simulation; binary phase comparator; performance improvement; phase locked loop; Adders; Circuit simulation; Clocks; Frequency synchronization; Frequency synthesizers; Low pass filters; Phase locked loops; Robust stability; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.780031
Filename
780031
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