DocumentCode :
2999201
Title :
Algorithmic Design of High-Precision Low-Power Multi-Stage Decimation Filters
Author :
Zanjani, S. M Mortazavi ; Omam, S. Rahimian ; Fakhraie, S.M. ; Shoaei, O.
Author_Institution :
Dept. of ECE, Tehran Univ., Tehran
Volume :
2
fYear :
2006
fDate :
6-9 Aug. 2006
Firstpage :
184
Lastpage :
187
Abstract :
An algorithm for design of high-precision low- power decimation filters for DeltaSigma analog-to-digital converters is described. This algorithm has been applied to decimation filters with oversampling ratios of 32 to 256, passband ripples of 2 to 0.0003 dB, stopband attenuation of -30 to -120 dB, and passband edge of 0.35 fs to 0.454 fs, where fs is the output sampling rate. This paper then goes forward by presenting a multiplierless, low- power multi-stage digital filter for decimation in DeltaSigma converters. A four-stage decimation filter with down-sampling factor of 64 is developed. A multi-stage CIC (Cascaded Integrator-Comb) filter which reduces the sampling rate by 8 is used for the first stage. Two halfband filters and an FIR droop correction filter follow the CIC filter each reducing the sampling rate by two. Techniques to simultaneously achieve high performance and low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than -120 dB and the passband ripple is less than 0.0003 dB. The designed decimation filter is synthesized on standard cells of a 0.18 mum CMOS library. The designed and synthesized decimation filter contributes to a power consumption saving of 10.6% compared to the previous successful filters implemented on the same library.
Keywords :
CMOS integrated circuits; FIR filters; analogue-digital conversion; comb filters; delta-sigma modulation; low-power electronics; CMOS library; DeltaSigma analog-to-digital converters; FIR droop correction filter; cascaded integrator-comb filter; down-sampling factor; four-stage decimation filter; high-precision low-power multistage decimation filter; multistage CIC filter; multistage digital filter design; oversampling ratio; power consumption; sampling rate reduction; size 0.18 mum; stopband attenuation; Algorithm design and analysis; Analog-digital conversion; Attenuation; Digital filters; Energy consumption; Finite impulse response filter; Libraries; Passband; Power filters; Sampling methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location :
San Juan
ISSN :
1548-3746
Print_ISBN :
1-4244-0172-0
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2006.382240
Filename :
4267318
Link To Document :
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