Logic simulation and parallel processing

A statistical model is presented of parallel processing based on circuit activity defined as the average number of gates evaluated at a time step. The number of active gates in a processor is assumed to be a random variable with a binomial probability density function. The performance of the multiprocessor system is derived from the maximum order-statistic of these random variables. When the gates can be equally divided among the p processors, the lower bound on speedup is found to be a*p, where a is the average circuit activity. For unequal division of gates, the lower bound on speedup is less than a*p. Interestingly, for very low activity, speedups significantly higher than the lower bounds are possible.<>