Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations

Interest in subthreshold design has increased due to the emergence of systems that require ultra-low power and the ever increasing leakage currents (now used to drive logic). Subthreshold sacrifices speed for power creating a clear divide between designing for high speed and ultra-low power. It might be beneficial to allow subthreshold circuits to operate in super-threshold, depending on processing needs. In this paper, the feasibility of optimizing device sizes for both subthreshold and above threshold operations is considered. In addition body biasing techniques that could facilitate bridging the speed gap are presented Device sizing for circuits of the subthreshold region is examined with the view that these circuits could be optimized for subthreshold but also operate effectively in super-threshold. In an effort to attain optimal performance (speed-power), an operating region is identified in terms of the energy-delay product. To enhance the operating speed of both subthreshold and super-threshold circuits, a novel body biasing technique termed tunable body biasing (TBB), is introduced This approach leads to increased operating frequencies particularly in subthreshold operation and shows no performance degradation at voltages above threshold, hence bridging of the speed gap. Post layout simulations of circuits ranging from simple to more complex ones enable for effective evaluation of optimal device sizing and identifying the optimal power-speed operational region. Simulations have been performed at a modest 180 nm technology node and circuits show optimal operating regions ranging from 0.5 to 1.1 V. Further more results indicate that the TBB approach for an inverter triples speed and has a 60 percent lower EDP while dissipating just 28 percent more energy than a traditionally biased approach (pMOS bulk at VDD and nMOS bulk at Vss).