Title :
Performance enhancement of partially- and fully-depleted strained-SOI MOSFETs and characterization of strained-Si device parameters
Author :
Numata, T. ; Irisawa, T. ; Tezuka, Taro ; Koga, James ; Hirashita, N. ; Usuda, Koji ; Toyoda, E. ; Miyamura, Y. ; Sugiyama, N.
Author_Institution :
MIRAI-ASET, Kawasaki, Japan
Abstract :
This paper demonstrates the successful fabrication of strained-SOI MOSFETs using SiGe on insulator (SGOI) substrates. 200mm SGOI wafer with Ge content of 30% is fabricated by Ge condensation technique. The performance enhancement over 14% is obtained in gate length of 70 nm. Furthermore, fully-depleted strained-SOI MOSFETs with back gate is demonstrated. Thin strained-Si layer can suppress the abnormal off leakage current due to the enhancement impurity diffusion.
Keywords :
Ge-Si alloys; MOSFET; condensation; silicon-on-insulator; substrates; Ge condensation technique; SiGe on insulator substrates; enhancement impurity diffusion; fully-depleted strained-SOI MOSFET; leakage current; partially-depleted strained-SOI MOSFET; strained-Si device parameters; Capacitive sensors; Ceramics; Fabrication; Germanium silicon alloys; MOSFETs; Metal-insulator structures; Pulse measurements; Rough surfaces; Silicon germanium; Surface roughness;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419100
