SRAM design for nanoscale technology with Dynamic Vth and dynamic standby voltage for leakage reduction

Present mobile applications demand for devices with low power and high speed. With continuous technology scaling power dissipation due to leakage currents has became biggest challenges of VLSI industry in designing of these high speed and low power devices. With projected large memory con-tent of future systems on chip devices, it is important to consider the leakage current in Static Random Access Memory (SRAM) structures. Literature contains various proposed leakage current reduction techniques for SRAM cell such as Data retention gated ground scheme, Dynamic threshold, Multi threshold SRAM, Sleep transistor based SRAM etc. This work focuses on design of SRAM cell with dynamic V_th and dynamic standby voltage to mitigate the leakage power dissipation. Simulation results show significant reduction in power dissipation in standby mode of SRAM cell.