DocumentCode
2999498
Title
Very fast chip-level thermal analysis
Author
Nakabayashi, Keiji ; Nakabayashi, Tamiyo ; Nakajima, Kazuo
Author_Institution
Nara Inst. of Sci. & Technol., Nara
fYear
2007
fDate
17-19 Sept. 2007
Firstpage
82
Lastpage
87
Abstract
We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.
Keywords
C language; Laplace equations; VLSI; finite difference methods; thermal analysis; C program; VLSI; chip-level thermal analysis; finite difference equations; mother board; two dimensional Laplace equations; Conducting materials; Finite difference methods; Heat sinks; Heat transfer; Laplace equations; Large-scale systems; Silicon; Thermal conductivity; Thermal engineering; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Thermal Investigation of ICs and Systems, 2007. THERMINIC 2007. 13th International Workshop on
Conference_Location
Budapest
Print_ISBN
978-2-35500-002-7
Type
conf
DOI
10.1109/THERMINIC.2007.4451752
Filename
4451752
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