80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity

Author

Choi, Woo Young ; Song, Jae Young ; Choi, Byung Yong ; Lee, Jong Duk ; Park, Young June ; Park, Byung-Gook

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

203

Lastpage

206

Abstract

We demonstrate an 80nm self-aligned complementary I-MOS for the first time by using double sidewall spacer, elevated drain structure and RTA process. It shows a normal transistor operation with small subthreshold swing which ranges from 5.5 to 12.2mV/dec at room temperature. The n- and p-channel I-MOS had an ON/OFF current of 394.1/0.3μA and 355.4/8.9μA per μm, respectively. We also investigate the effect of L₁ variation to device characteristics and finally show the feasibility of the I-MOS as an amplifier with high linearity.

Keywords

CMOS integrated circuits; MOSFET; amplifiers; nanoelectronics; rapid thermal annealing; 0.3 muA; 355.4 muA; 394.1 muA; 8.9 muA; 80 nm; L₁ variation; RTA process; double sidewall spacer; elevated drain structure; high linearity amplifier; n-channel I-MOS; normal transistor operation; on-off current; p-channel I-MOS; room temperature; self-aligned complementary I-MOS; small subthreshold swing; Fabrication; Linearity; MOSFETs; PIN photodiodes; Physics; Rapid thermal annealing; Rapid thermal processing; Semiconductor optical amplifiers; Temperature distribution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419108

Filename

1419108