Title :
Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs
Author :
Goto, K. ; Satoh, S. ; Ohta, H. ; Fukuta, S. ; Yamamoto, T. ; Mori, T. ; Tagawa, Y. ; Sakuma, T. ; Saiki, T. ; Shimamune, Y. ; Katakami, A. ; Hatada, A. ; Morioka, H. ; Hayami, Y. ; Inagaki, S. ; Kawamura, K. ; Kim, Y. ; Kokura, H. ; Tamura, N. ; Horiguch
Author_Institution :
Fujitsu Ltd., Tokyo, Jordan
Abstract :
Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120μA/μm and 690μA/μm at Vdd=1V/Ioff=100nA/μm, respectively. This is the best drive current among the recent reports.
Keywords :
MOSFET; bending; coating techniques; insulating thin films; multilayers; nanotechnology; silicon compounds; 1 V; 37 nm; 45 nm; 65 nm; 65nm node high performance MPU; SiN; SiN film; channel strain; drive current; multilayer deposition; nMOS gate; nMOSFET; pMOSFET; strain-enhancing laminated SiN; technology booster; wafer bending problem; Capacitive sensors; Electronic mail; Etching; MOS devices; MOSFET circuits; Roads; Silicon compounds; Stress control; Substrates; Tensile stress;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419111
