Title :
A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films
Author :
Pidin, S. ; Mori, T. ; Inoue, K. ; Fukuta, S. ; Itoh, N. ; Mutoh, E. ; Ohkoshi, K. ; Nakamura, R. ; Kobayashi, K. ; Kawamura, K. ; Saiki, T. ; Fukuyama, S. ; Satoh, S. ; Kase, M. ; Hashimoto, K.
Author_Institution :
Adv. LSI Dev. Div., Fujitsu Ltd., Tokyo, Japan
Abstract :
A novel CMOS architecture utilizing tensile/compressive silicon nitride capping layers to induce tensile/compressive strain in NMOSFET/PMOSFET channel regions was developed. NMOSFET device delivers 1.05mA/μm on-current for 70nA/μm off-current at IV drain voltage. PMOS device exhibits peak 66% increase of linear drain current and 55% increase of saturation current. It was shown that drain current improvements both for N- and PMOSFETs strongly correlate with channel doping levels. Therefore, advanced methods of shallow and low resistance junction formation are required for maintaining low channel doping concentration and efficiently utilizing channel strain at sub-40nm gate length.
Keywords :
CMOS integrated circuits; MOSFET; coating techniques; compressive strength; doping; insulating thin films; nanotechnology; silicon compounds; tensile strength; IV drain voltage; NMOSFET channel regions; PMOSFET channel regions; SiN; channel doping levels; channel strain; compressive strain; high compressive silicon nitride films; high tensile silicon nitride films; linear drain current; low channel doping concentration; low resistance junction formation; saturation current; selective deposition; silicon nitride capping layers; strain enhanced CMOS architecture; tensile strain; Compressive stress; Doping; MOS devices; MOSFET circuits; Semiconductor films; Silicides; Silicon; Tensile strain; Tensile stress; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419112
