Title :
Sequential synthesis using S1S
Author :
Aziz, A. ; Balarin, F. ; Brayton, R. ; Sangiovanni-Vincentelli, A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
We present a mathematical framework for analyzing the synthesis of interacting, finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems.
Keywords :
finite state machines; logic CAD; logic design; sequential circuits; FSM network behavior; S1S; finite state systems; sequential synthesis; Automata; Design automation; Design optimization; Digital systems; Laboratories; Logic; Modems; Network synthesis; Process design; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-8200-0
DOI :
10.1109/ICCAD.1995.480192
