Static Noise Margin of 6T SRAM Cell in 90-nm CMOS

Author

Arandilla, Christiensen D C ; Alvarez, Anastacia B. ; Roque, Christian Raymund K

Author_Institution

Electr. & Electron. Eng. Inst., Univ. of the Philippines-Diliman, Quezon City, Philippines

fYear

2011

fDate

March 30 2011-April 1 2011

Firstpage

534

Lastpage

539

Abstract

This paper examines the factors that affect the Static Noise Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while varying several parameters that affect SRAM operations. These parameters are temperature, threshold voltage, supply voltage, cell ratio, pull-up ratio, and process corner variations. The simulation results were found to be in agreement with the model derived by Seevinck et al. which is based on the square law device model.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit modelling; integrated circuit noise; 6T static random access memory cell; CMOS technology; and process corner variations; cell ratio; pull-up ratio; size 90 nm; square law device model; static noise margin; supply voltage; threshold voltage; Inverters; Noise; Noise measurement; Random access memory; Threshold voltage; Transistors; Voltage measurement; 6T SRAM stability; hold margin; n-curve; read margin; static noise margin; write margin;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Modelling and Simulation (UKSim), 2011 UkSim 13th International Conference on

Conference_Location

Cambridge

Print_ISBN

978-1-61284-705-4

Electronic_ISBN

978-0-7695-4376-5

Type

conf

DOI

10.1109/UKSIM.2011.108

Filename

5754277