Title :
Reuse of VLSI layout topology by parametric BSG
Author :
Wu, Zhonglin ; Sakanushi, Keishi ; Kajitani, Yoji
Author_Institution :
Dept. of Commun. & Integrated Syst., Tokyo Inst. of Technol., Japan
Abstract :
In reuse of a VLSI layout design, we first determine the information to abstract from a given design, and then prepare a data structure to store it. Since a further optimization is required in the new environment, the data structure must be flexible to accept a change in the data. In this paper, the floorplan of a given layout is focused on. It is characterized by a topological property, called the seg-based 4-direction. The parametric BSG (PBSG) is proposed as the data structure. An elegant procedure to map the seg-based 4-direction into PBSG of minimum size is given. Merits of using PBSG in reuse are discussed
Keywords :
VLSI; circuit layout CAD; circuit optimisation; data structures; integrated circuit layout; network topology; PBSG algorithm; VLSI layout topology reuse; data structure; floorplan; layout design; optimization; parametric BSG; seg-based 4-direction; topological property; Circuits; Communications technology; Compaction; Data structures; Topology; Very large scale integration; Wires;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913646
