Superior metal step coverage and dielectric quality in a simple two-level metal 1.0 μm CMOS technology

Author

Fieber, C.A. ; Martin, E.P. ; Chew, H.Z. ; Hills, G.W. ; Selamoglu, N. ; Lytle, S.A.

Author_Institution

AT&T Bell Lab., Allentown, PA, USA

fYear

1989

fDate

12-13 Jun 1989

Firstpage

55

Lastpage

61

Abstract

A two-level metal process for a fourth-generation 1.0-μm CMOS technology has been developed which yields superior aluminum step coverages and high-quality dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and resist-etchback planarization of plasma-enhanced TEOS for dielectric II. Also featured are a tapered aluminum I profile and modified contact window and via etch profiles. Defect density and electromigration data predict excellent yield and reliability for this process

Keywords

CMOS integrated circuits; aluminium; dielectric thin films; integrated circuit technology; metallisation; 1 micron; Al; B2O3-P2O5-SiO2; BPSG; CMOS technology; contact window; defect density; dielectric quality; electromigration; high throughput operations; metal step coverage; plasma-enhanced TEOS; reliability; resist-etchback planarization; two-level metal process; via etch profiles; yield; Aluminum; CMOS process; CMOS technology; Dielectric materials; Inorganic materials; Planarization; Plasma applications; Plasma density; Plasma materials processing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1989.78006

Filename

78006