Author :
Heinemann, B. ; Barth, R. ; Bolze, D. ; Drews, J. ; Formanek, P. ; Grabolla, T. ; Haak, U. ; Hoppner, W. ; Kuck, B. ; Kurps, R. ; Marschmeyer, S. ; Richter, H.H. ; Rucker, Holger ; Schley, P. ; Schmidt, Dan ; Winkler, Wolfgang ; Wolansky, Dirk ; Wulf, H.E
Abstract :
We present a new collector construction for high-speed SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector region. The impact of the collector module on RF performance is demonstrated in separate bipolar processes for npn and pnp devices. A minimum gate delay of 3.2ps was achieved for CML ring oscillators with npn transistors featuring fT/fmax values of 300GHz/250GHz at BVCEO = 1.8V. For pnp devices with fT/fmax values of 135GHz/140GHz at BVCEO = 2.5V a gate delay of 5.9ps is demonstrated. Further vertical scaling of the doping profiles increases fT to 380GHz at BVCEO=1.5V for npn´s and 155GHz at BVCEO = 2.3V for pnp´s, but ring oscillator speed and fmax degraded.
Keywords :
Ge-Si alloys; doping profiles; etching; heterojunction bipolar transistors; millimetre wave bipolar transistors; oscillators; 1.8 V; 135 GHz; 140 GHz; 2.5 V; 250 GHz; 3.2E-12 s; 300 GHz; CML ring oscillators; RF performance; SiGe:C; bipolar processes; collector module; collector region underetching; doping profile; heterojunction bipolar transistor; high-speed SiGe:C HBT; low-parasitic collector construction; minimum gate delay; npn devices; npn transistors; parasitic base-collector capacitance; pnp devices; vertical scaling; Delay; Doping profiles; Epitaxial growth; Etching; Germanium silicon alloys; Heterojunction bipolar transistors; Implants; Parasitic capacitance; Ring oscillators; Silicon germanium;
