JHDL Implementation of a BIST Scheme for Testing the Look-Up Tables of SRAM Based FPGAs

Built in self test for FPGAs has become an important area of research over the years. The current research focuses on the use of JHDL as an implementation tool for BIST. The research spans the design, simulation and JHDL implementation of a BIST scheme for testing the Look-Up Tables of a Xilinx SRAM based Spartan II FPGA. To the best of our knowledge, this is the first attempt by any researcher in using JHDL for implementing BIST on FPGAs.