Title :
Aggressively scaled (0.143 μm2) 6T-SRAM cell for the 32 nm node and beyond
Author :
Fried, D.M. ; Hergenrother, J.M. ; Topol, A.W. ; Chang, L. ; Sekaric, L. ; Sleight, J.W. ; McNab, S.J. ; Newbury, J. ; Steen, S.E. ; Gibson, G. ; Zhang, Y. ; Fuller, N.C.M. ; Bucchignano, J. ; Lavoie, C. ; Cabral, C., Jr. ; Canaperi, D. ; Dokumaci, O. ; F
Author_Institution :
Syst. & Technol. Group, IBM Semicond. R&D Center, Hopewell Junction, NY, USA
Abstract :
A 0.143 μm2 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (VT) and cell beta ratio (β) are optimized for cell stability at these aggressive ground rules. The 0.143 μm2 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at VDD=1.0 V.
Keywords :
SRAM chips; circuit optimisation; cobalt compounds; copper; electron beam lithography; integrated circuit interconnections; isolation technology; nanotechnology; photolithography; silicon-on-insulator; tungsten; 1 V; 15 nm; 25 nm; 45 nm; 50 nm; 6T-SRAM cell; CoSi; Cu; SOI layer; Si; W; cell beta ratio; damascene copper interconnect; device threshold voltage; electron-beam lithography; extremely thin cobalt disilicide; optical lithography; physical gates; planar SOI technology; shallow trench isolation; static noise margin; tungsten plug contacts; ultra-narrow spacers; Cobalt; Copper; Isolation technology; Lithography; Plugs; Space technology; Stability; Threshold voltage; Tungsten; Ultraviolet sources;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419127
