DocumentCode
2999947
Title
A minimally redundant radix-4 systolic array for high performance IIR filtering
Author
Walke, R.L. ; Evans, R.A.
Author_Institution
DRA Malvern, UK
fYear
1993
fDate
20-22 Oct 1993
Firstpage
168
Lastpage
176
Abstract
The authors consider the radix-4 implementation of a parallel multiplier accumulator suitable for performing recursive filtering. A new parallel multiplier is presented which exploits the minimally redundant radix-4 number representation to nearly halve the area of previous radix-2 design and provide a 20% speed advantage. The architecture supports fine grain pipelining and has a computation time which is independent of wordlength
Keywords
IIR filters; digital arithmetic; multiplying circuits; pipeline arithmetic; programmable filters; recursive filters; redundant number systems; systolic arrays; fine grain pipelining; high performance IIR filtering; minimally redundant; parallel multiplier accumulator; radix-4 implementation; radix-4 systolic array; recursive filtering; Arithmetic; Array signal processing; Computer architecture; Delay; Feedback loop; Filtering; IIR filters; Parallel architectures; Pipeline processing; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location
Veldhoven
Print_ISBN
0-7803-0996-0
Type
conf
DOI
10.1109/VLSISP.1993.404490
Filename
404490
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