Author :
Nackaerts, A. ; Ercken, M. ; Demuynck, S. ; Lauwers, A. ; Baerts, C. ; Bender, H. ; Boulaert, W. ; Collaert, Nadine ; Degroote, B. ; Delvaux, C. ; de Marneffe, J.F. ; Dixit, Abhishek ; De Meyer, K. ; Hendrickx, Etienne ; Heylen, N. ; Jaenen, P. ; Laidler,
Abstract :
This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314μm2 build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.
Keywords :
SRAM chips; copper; nanotechnology; nickel compounds; ultraviolet lithography; 0.6 V; 0.75NA 193nm lithography; 193 nm; 35 nm; 45 nm; 6T-SRAM cell; 70 nm; Cu; HALO implants; HDD spacer; NiSi; fabrication process; low-k BEOL; low-tilt extension; physical gate length; static noise margin; tall triple-gate device; Etching; Fabrication; FinFETs; Implants; Layout; Lighting; Lithography; Optical design; Random access memory; Tin;
