A programmable application-specific VLSI architecture and implementation for speech word-recognizer

In this paper, the efficient and flexible VLSI architecture and implementation for the voice word-recognizer processor are presented. In order to achieve a flexible and efficient VLSI realization, we use a programmable with specific core design strategy which incorporates the best aspects of both programmable and application specific signal processors to achieve high speed, high accuracy and efficient hardware realization for the word-recognizer. On the whole, the single chip is fabricated in 0.8 μm double-metal CMOS technology after the physical design and circuit verification. The chip can process 40 MHz sampled data and it contains about 70000 transistors which occupy 0.62.×0.60 cm² area