DocumentCode
3000150
Title
Sequential power per area optimization of multichannel neural recording interface based on dual quadratic programming
Author
Zjajo, Amir ; Galuzzi, Carlo ; van Leuken, Rene
Author_Institution
Circuits & Syst. Group, Delft Univ. of Technol., Delft, Netherlands
fYear
2015
fDate
22-24 April 2015
Firstpage
9
Lastpage
12
Abstract
In this paper, we propose a novel method for power per area optimization under yield constrains in multichannel neural recording interface. Using a sequence of minimizations with iteratively-generated low-dimensional subspaces, our approach renders consistently improved power per area ratio and imposes no restrictions on the distribution of process parameters or how the data enters the constraints. The experimental results, obtained on neural recording interface circuits in CMOS 90nm technology, demonstrate power savings of up to 26% and area of up to 22% without yield penalty.
Keywords
CMOS integrated circuits; brain-computer interfaces; iterative methods; minimisation; neurophysiology; quadratic programming; CMOS technology; dual quadratic programming; iterative-generated low-dimensional subspaces; minimizations; multichannel neural recording interface; sequential power per area optimization; yield constrains; Brain-computer interfaces; CMOS integrated circuits; Electrodes; Minimization; Neurons; Noise; Optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Engineering (NER), 2015 7th International IEEE/EMBS Conference on
Conference_Location
Montpellier
Type
conf
DOI
10.1109/NER.2015.7146547
Filename
7146547
Link To Document