Title :
Skew-Tolerant Domino Techniques for High-Speed Baugh-Wooley Multiplier Circuit Design
Author :
Tu, Steve Hung-Lung ; Yen, Chih-Hung
Author_Institution :
Fu Jen Catholic Univ., Taipei
Abstract :
The conventional architecture suffers significant timing overhead due to system clock skew and logic path unbalance, which in turn decreases the performance of a circuit. This paper presents a design of high-speed Baugh-Wooley multiplier based on skew-tolerant domino. From simulation results, it is demonstrated that the performance is improved.
Keywords :
CMOS logic circuits; high-speed integrated circuits; integrated circuit design; multiplying circuits; pipeline arithmetic; timing; CMOS circuit; high-speed Baugh-Wooley multiplier circuit design; logic path unbalance; skew-tolerant domino techniques; system clock skew; Circuit simulation; Circuit synthesis; Clocks; Computational modeling; Design engineering; Electronic mail; Latches; Logic circuits; Logic design; Timing; Skew-tolerant domino; clock skew; domino circuit; static circuit;
Conference_Titel :
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location :
San Juan
Print_ISBN :
1-4244-0172-0
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2006.382303
