A Self-Timed 16-bit Multiplier for Low-Power Low-Frequency Applications

A comprehensive study of spurious activity propagation, based on transistor-level simulations targeting a 0.18 CMOS process, is carried out in traditional multiplier architectures (Carry-Save, Carry-Save with Booth receding and Wallace tree). The results suggest to implement self-timed multipliers, i.e. multipliers in which partial products are triggered by an independent delay line: they have the property of suppressing unnecessary switching activity. They are discussed in terms of area occupation and, especially, power dissipation and Energy- Delay-Product (EDP). After that, a new self-timed multiplier architecture is introduced. Transistor-level simulations point out a dissipation of 2.0 muW/MHz against 4.8 muW/MHz of a recently published self-timed multiplier and 4.1 muW/MHz of the most efficient traditional architecture (Wallace), with a reduced 5% area overhead compared to the latter one.