• DocumentCode
    3000321
  • Title

    A multi-cycle operational signal processing core for an adaptive equalizer for magnetic system application

  • Author

    Kojima, Hirotsugu ; Tanaka, Satoshi ; Okada, Yutaka ; Hikage, Tetsuro ; Nakazawa, Fumio ; Matsushige, Hiromi ; Miyasaka, Hideki ; Hanamura, Shoji

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • fYear
    1993
  • fDate
    20-22 Oct 1993
  • Firstpage
    150
  • Lastpage
    157
  • Abstract
    An adaptive equalizer has been developed using multi-cycle operational signal processing cores; an equalizing filtering core and a coefficient calculating core including an IIR stabilizing filter. The authors propose an IIR stabilizing filter core and discuss the stability of the adaptive equalizer. The proposed IIR filter core needs less than half number of gates of an FIR filter core realized in a straight ford way of design, and it keeps excellent stability. Each core, an equalizing filtering core and a coefficient calculating core, operates seven cycle time of 20ns during a sampling period. The number of gates was a third of straight ford design where one operator is employed during a sampling period. The proposed architecture made it possible to realize a fully digital equalizer with maximum likelihood detection and clock recovery
  • Keywords
    CMOS digital integrated circuits; IIR filters; VLSI; adaptive equalisers; adaptive signal processing; application specific integrated circuits; digital filters; digital magnetic recording; maximum likelihood detection; CBIC; CMOS; IIR stabilizing filter; adaptive equalizer; clock recovery; coefficient calculating core; equalizing filtering core; for magnetic system application; fully digital equalizer; maximum likelihood detection; multicycle operational signal processing core; rounding; wordlengths; Adaptive equalizers; Adaptive filters; Adaptive signal processing; Clocks; Filtering; Finite impulse response filter; IIR filters; Maximum likelihood detection; Sampling methods; Stability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Signal Processing, VI, 1993., [Workshop on]
  • Conference_Location
    Veldhoven
  • Print_ISBN
    0-7803-0996-0
  • Type

    conf

  • DOI
    10.1109/VLSISP.1993.404492
  • Filename
    404492