Integration of ALD TaN barriers in porous low-k interconnect for the 45 nm node and beyond; solution to relax electron scattering effect

The down scaling of interconnect wiring is facing serious hurdles below 100 nm feature size due to a non-linear resistivity increase with decreasing line width. In order to investigate the increase of copper resistivity for the future technology nodes a novel hard mask spacer patterning technology was used to fabricate very narrow Cu inlaid interconnect trenches in a porous low-k dielectric. ALD TaN and PVD TaN films were deposited on a porous SiOC CVD dielectric material that received a pore sealing treatment prior to barrier deposition. The parametrical test results showed that in-diffusion of ALD reactants did not take place resulting in an improved RC performance without degradation of k-value. The effect of the decreasing line width on reliability performance of barrier and porous dielectric was studied by electromigration (EM) and biased thermal stress (BTS) measurements. The extendibility and scalability of atomic layer deposition was shown to be attractive for future process nodes with smaller dimensions.