Challenge of low-k materials for 130, 90, 65 nm node interconnect technology and beyond

Author

Miyajima, H. ; Watanabe, K. ; Fujita, K. ; Ito, S. ; Tabuchi, K. ; Shimayama, T. ; Akiyama, K. ; Hachiya, T. ; Higashi, K. ; Nakamura, N. ; Kajita, Akihiro ; Matsunaga, N. ; Enomoto, Y. ; Kanamura, R. ; Inohara, M. ; Honda, K. ; Kamijo, H. ; Nakata, R. ;

Author_Institution

Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan

fYear

2004

fDate

13-15 Dec. 2004

Firstpage

329

Lastpage

332

Abstract

In order to realize highly reliable low-k/Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65 nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replaced by the hybrid-DD structure with PAr/SiOC stack films. It shows high extendibility to the next generation using newly developed technologies, such as eBeam cure and damage restoration techniques.

Keywords

copper; integrated circuit interconnections; interface structure; logic devices; nanoelectronics; phosphorus compounds; silicon compounds; thin film circuits; 130 nm; 65 nm; 90 nm; BEOL structures; PAr-SiOC; damage restoration techniques; eBeam cure; hybrid-DD structure; interconnect technology; logic devices; low-k materials; low-k/Cu interconnects; monolithic dual damascene structure; stack films; Adhesives; Design optimization; Dielectric materials; Logic devices; Materials reliability; Plasma applications; Plasma materials processing; Plasma properties; Process design; Resists;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Print_ISBN

0-7803-8684-1

Type

conf

DOI

10.1109/IEDM.2004.1419147

Filename

1419147