Title :
A Novel Delay Model of CMOS VLSI Circuits
Author :
Chang, Jian ; Johnson, Louis G.
Author_Institution :
Oklahoma State Univ., Stillwater
Abstract :
In this paper, a piecewise linear delay model which can predict the accurate propagation delay of the general CMOS VLSI circuitry is presented. The model takes into account the effect of the slope of the input waveform on the delay. By using simple piecewise linear current model and piecewise linear channel charge storage model, it is possible to simulate the modern digital logic circuits in a reasonable amount of time. Excellent agreement with SPICE simulation has been observed in CMOS inverter and 2-input NAND gate cases.
Keywords :
CMOS logic circuits; SPICE; VLSI; delay circuits; integrated circuit design; logic design; piecewise linear techniques; CMOS VLSI circuits; CMOS inverter; NAND gate; SPICE simulation; digital logic circuits; piecewise linear channel charge storage model; piecewise linear delay model; Circuit simulation; Delay effects; Delay lines; Logic circuits; Piecewise linear techniques; Predictive models; Propagation delay; SPICE; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location :
San Juan
Print_ISBN :
1-4244-0172-0
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2006.382318
