DocumentCode
3000730
Title
PBuf: An On-Chip Packet Transfer Engine for MONARCH
Author
Bhatti, Rashed Zafar ; Steele, Craig ; Draper, Jeff
Author_Institution
Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA
Volume
2
fYear
2006
fDate
6-9 Aug. 2006
Firstpage
531
Lastpage
535
Abstract
This paper describes the architecture and implementation of an on-chip packet interface/router called the packet buffer (PBuf) employed in the MOrphable Networked microARCHitecture (MONARCH). This work provides a brief overview of MONARCH and its subsystems to provide motivation for the PBuf design. MONARCH employs a hierarchy with various levels of address spaces. To connect the subsystems and keep the network complexities low, communication packets undergo an address translation process while passing across the address space boundaries. The PBuf provides protected translation in the midst of superior and inferior address spaces while also serving as an on-chip packet switching router. Additional features, such as its 6 memory to memory block transfer (MMBT) engines, enable it to provide high rate data transfer capabilities.
Keywords
buffer storage; integrated circuit design; integrated circuit interconnections; microprocessor chips; network routing; MONARCH; PBuf; address space boundaries; address translation process; data transfer capabilities; memory to memory block transfer engines; morphable networked microarchitecture; node interconnection; on-chip packet interface/router; on-chip packet switching router; on-chip packet transfer engine; packet buffer design; Arithmetic; Bandwidth; Computer architecture; Concurrent computing; Embedded computing; Engines; Network-on-a-chip; Packet switching; Protection; Tiles;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location
San Juan
ISSN
1548-3746
Print_ISBN
1-4244-0172-0
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2006.381784
Filename
4267408
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