DocumentCode :
3000750
Title :
Clustering to improve bi-partition quality and run time
Author :
Tumbush, Gregory ; Bhatia, Dinesh
Author_Institution :
Res. Lab., Wright-Patterson AFB, OH, USA
Volume :
6
fYear :
1999
fDate :
36342
Firstpage :
145
Abstract :
Circuit partitioning is a very extensively studied problem. Traditional heuristic methods used to solve these problems degrade in performance when the problem size becomes large. Clustering has been proposed as a method to reduce the problem size, allowing the problem to be solved faster and with more accuracy. We proposed a novel bipartitioning method based on a mathematical formulation of the problem which can be solved using commercial combinatorial optimization (CO) tools. In this paper we continue to formulate the problem as a nonlinear program (NLP) but also apply clustering to determine if run-time and quality can be improved
Keywords :
circuit layout CAD; circuit optimisation; graph theory; network topology; nonlinear programming; bi-partition quality; bipartitioning method; circuit partitioning; combinatorial optimization; network topology; nonlinear program; problem size; run time; Aerospace electronics; Circuits; Clustering algorithms; Degradation; Design automation; Force sensors; Laboratories; Optimization methods; Partitioning algorithms; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
Type :
conf
DOI :
10.1109/ISCAS.1999.780116
Filename :
780116
Link To Document :
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