Title :
On VLSI decompositions for deBruijn graphs
Author :
Yamada, Toshinori ; Imai, Satoshi ; Ueno, Shuichi
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan
Abstract :
A VLSI decomposition of a graph G is a collection of isomorphic vertex-disjoint subgraphs (called building blocks) of G which together span G. This paper gives a necessary condition and a sufficient condition for a graph to be a building block for deBruijn graphs, which are used to build Viterbi decoders
Keywords :
VLSI; Viterbi decoding; graph theory; integrated circuit layout; VLSI decompositions; Viterbi decoders; building blocks; deBruijn graphs; isomorphic vertex-disjoint subgraphs; Coupling circuits; Decoding; Sufficient conditions; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780121
