DocumentCode
3001004
Title
Functionally-aware Partitioning of Discrete Signal Transforms for Distributed Hardware Architectures
Author
Arce-Nazario, Rafael A. ; Jimenez, Manuel ; Rodríguez, Domingo
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Puerto Rico at Mayaguez, Mayaguez
Volume
2
fYear
2006
fDate
6-9 Aug. 2006
Firstpage
590
Lastpage
594
Abstract
A high-level partitioning methodology is introduced, which uses formulation-level discrete signal transform properties to provide improved results for their partitioning to distributed hardware architectures. We discuss how discrete signal transform characteristics were taken into account to focus design exploration during partitioning. Additionally, a description is given of the experiments conducted to determine the effect of formulation-level properties on solution quality. Perceived patterns in experimental results were used to generate ´partition- friendly´ formulations for distributed hardware architectures.
Keywords
discrete transforms; field programmable gate arrays; high level synthesis; logic partitioning; discrete signal transform characteristics; distributed hardware architectures; formulation-level discrete signal transform; functionally-aware partitioning methodology; high-level partitioning methodology; multiFPGA boards; Computer architecture; Discrete transforms; Distributed computing; Electric breakdown; Flexible printed circuits; Hardware; Optimization methods; Partitioning algorithms; Signal design; Spirals;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on
Conference_Location
San Juan
ISSN
1548-3746
Print_ISBN
1-4244-0172-0
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2006.381799
Filename
4267423
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