An analytical, transistor-level energy model for SRAM-based caches

Author

Bellas, Nikos ; Hajj, Ibrahim ; Polychronopoulos, Constantine

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

6

fYear

1999

fDate

36342

Firstpage

198

Abstract

In this paper, we present a detailed, transistor-level energy model of on-chip caches that use SRAM technology. The energy estimation is based on the work by by Wilson and Jouppi [1994], in which they propose a timing analysis model for SRAM-based caches. Our model uses runtime information of the cache utilization (number of accesses, number of hits, misses, input statistics etc.) gathered during simulation, as well as complexity and internal cache organization parameters (cache size, block size, associativity, banking etc.)

Keywords

SRAM chips; cache storage; integrated circuit design; integrated circuit modelling; SRAM-based caches; associativity; block size; cache size; cache utilization; complexity; energy estimation; input statistics; internal cache organization parameters; on-chip caches; runtime information; transistor-level energy model; Analytical models; Banking; Circuit simulation; Decoding; Electronic mail; Laboratories; Random access memory; Statistics; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780129

Filename

780129