Interconnect-Centric High Level Synthesis for Enhanced Layouts with Reduced Wire Length

In deep sub-micron (DSM) technologies, the interconnect significantly impacts the design performance and reliability: a considerable fraction of the total circuit power is consumed by interconnects, crossing the global interconnects requires multiple clock cycles and the wire capacitance directly affects the noise levels. This paper introduces a novel high- level synthesis (HLS) methodology that exploits architectural optimizations that lead to final circuits (layouts) with enhanced interconnect power and delay without introducing any overhead. We present a new interconnect-centric scheduling algorithm and a global binding that combines the functional unit binding and register binding. These routines generate circuits with improved interconnect through minimizing the nets (the number and fan-out) and steering logic. The binding process achieves this by considering clusters of operations as compatible candidates instead of individual operations, while the scheduling makes assignments that maximize the cluster compatibility. The experiments with several synthesis benchmarks show the effectiveness of the approach in reducing the total number, the average fan-out and the length of the nets without introducing any logic overhead. We achieved an average reduction of approximately 16% in total wire length compared to the layout of the designs generated by conventional synthesis tools.