Modeling of accumulation MOS capacitors for analog design in digital VLSI processes

Author

Pavan, Shanthi ; Tsividis, Yannis ; Nagaraj, Krishnaswamy

Author_Institution

Texas Instrum., Warren, NJ, USA

Volume

6

fYear

1999

fDate

36342

Firstpage

202

Abstract

In this paper, we present an explicit model for the MOS capacitor in accumulation and compare it with device simulation and measurement results. The model is physics based and tracks substrate doping concentration and temperature, and incorporates the polysilicon gate depletion effect. Harmonic distortion generated when the proposed model is used in circuit simulation agrees with that obtained by using a very closely spaced piecewise linear model generated by device simulation

Keywords

CMOS integrated circuits; MOS capacitors; circuit simulation; integrated circuit design; integrated circuit modelling; mixed analogue-digital integrated circuits; piecewise linear techniques; accumulation MOS capacitors; analog design; circuit simulation; device simulation; digital VLSI processes; explicit model; harmonic distortion; it with device simulation and measurement results. The model is p; physics based model; polysilicon gate depletion effect; substrate doping concentration; very closely spaced piecewise linear model; CMOS process; CMOS technology; Capacitance; Circuit simulation; Doping; MOS capacitors; Semiconductor device modeling; Semiconductor process modeling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.780130

Filename

780130