Title :
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications
Author :
Boeuf, F. ; Arnaud, F. ; Basso, M.T. ; Sotta, D. ; Wacquant, F. ; Rosa, J. ; Bicais-Lepinay, N. ; Bernard, H. ; Bustos, J. ; Manakli, S. ; Gaillardin, M. ; Grant, J. ; Skotnicki, T. ; Tavel, B. ; Duriez, B. ; Bidaud, M. ; Gouraud, P. ; Chaton, C. ; Morin,
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonstrated. GP nFET/pFET devices feature Ion= 820μA/μm/340 μA/μm at Ioff = 20nA/μm at Vdd=1.0V. RO features Tp < 10ps. LP devices feature Ion= 505 μA/μm 1240 μA/μm at Ioff = 0.1 nA/μm at Vdd= 1.2V. In addition, high-voltage 50A/2.5V devices are made to complete the CMOS platform.
Keywords :
CMOS integrated circuits; low-power electronics; nanotechnology; 2.5 V; 45 nm; 50 A; CMOS; LP devices; SiON gate oxide; conventional bulk approach; general purpose application; low power applications; low-cost platform; nFET/pFET devices; process induced strain; shallow junctions; Capacitive sensors; Data mining; Degradation; Gate leakage; High K dielectric materials; High-K gate dielectrics; Lead compounds; Performance loss; Power supplies; Silicon;
Conference_Titel :
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Print_ISBN :
0-7803-8684-1
DOI :
10.1109/IEDM.2004.1419177
