A Neural Network CMOS Circuit Implementation for Real-Time Halftoning Applications

We report on an underlying hardware approach to implement a neural network for real-time image halftoning. We present simulation and experimental results using a modified current starved comparator as the quantizing element that has a 40 fold reduction in pixel current over our previous designs. The neuron is self-biasing with error weighting achieved through current division to enable operation at a variety of bias voltages. The circuit is designed for integration with a flip-chip bonded photodiode array for imaging applications.