Title :
CMOS gate modeling based on equivalent inverter
Author :
Chatzigeorgiou, A. ; Nikolaidis, S. ; Tsoukalas, I. ; Koufopavlou, O.
Author_Institution :
Dept. of Comput. Sci., Aristotelian Univ. of Thessaloniki, Greece
Abstract :
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each case, taking into account the actual operating conditions of each device in the structure. The accuracy of the method is validated by the results for two submicron technologies and its efficiency as a technique that can improve existing timing simulators is demonstrated
Keywords :
CMOS logic circuits; circuit CAD; circuit simulation; logic CAD; logic gates; logic simulation; timing; CMOS gate modeling; conducting behavior; effective equivalent inverter; equivalent inverter; operating conditions; parallel connected transistors; parasitic behavior; serially connected transistors; submicron technologies; timing simulators; Circuit simulation; Computer science; Integrated circuit technology; Inverters; Physics; Semiconductor device modeling; Threshold voltage; Timing; Transconductance; Virtual manufacturing;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.780138
